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Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference
2010;2010 1691-4.

Reconfigurable embedded system architecture for next-generation Neural Signal Processing.

Karthikeyan Balasubramanian, Iyad Obeid
Author Information
  1. Karthikeyan Balasubramanian: Neural Instrumentation Lab, Temple University, Philadelphia, PA 19122, USA. bkintex@temple.edu
PMID: 21096398 DOI: 10.1109/IEMBS.2010.5626833

Abstract

This work presents a new architectural framework for next generation Neural Signal Processing (NSP). The essential features of the NSP hardware platform include scalability, reconfigurability, real-time processing ability and data storage. This proposed framework has been implemented in a proof-of-concept NSP prototype using an embedded system architecture synthesized in a Xilinx(®)Virtex(®)5 development board. The prototype includes a threshold-based spike detector and a fuzzy logic-based spike sorter.

MeSH Term

Action Potentials
Animals
Computing Methodologies
Electroencephalography
Equipment Design
Equipment Failure Analysis
Humans
Neurons
Signal Processing, Computer-Assisted
Journal Article Research Support, U.S. Gov't, Non-P.H.S.

Word Cloud

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