Multimodal 2D Ferroelectric Transistor with Integrated Perception-and-Computing-in-Memory Functions for Reservoir Computing.

Jiachao Zhou, Anzhe Chen, Yishu Zhang, Xinwei Zhang, Jian Chai, Jiayang Hu, Hanxi Li, Yang Xu, Xulang Liu, Ning Tan, Fei Xue, Bin Yu
Author Information
  1. Jiachao Zhou: College of Integrated Circuits, Zhejiang University, Hangzhou 310027, China. ORCID
  2. Anzhe Chen: College of Integrated Circuits, Zhejiang University, Hangzhou 310027, China.
  3. Yishu Zhang: College of Integrated Circuits, Zhejiang University, Hangzhou 310027, China. ORCID
  4. Xinwei Zhang: College of Integrated Circuits, Zhejiang University, Hangzhou 310027, China.
  5. Jian Chai: College of Integrated Circuits, Zhejiang University, Hangzhou 310027, China.
  6. Jiayang Hu: College of Integrated Circuits, Zhejiang University, Hangzhou 310027, China.
  7. Hanxi Li: College of Integrated Circuits, Zhejiang University, Hangzhou 310027, China. ORCID
  8. Yang Xu: College of Integrated Circuits, Zhejiang University, Hangzhou 310027, China.
  9. Xulang Liu: School of Computer Science and Engineering, Sun Yat-sen University, Guangzhou 528402, China.
  10. Ning Tan: School of Computer Science and Engineering, Sun Yat-sen University, Guangzhou 528402, China.
  11. Fei Xue: College of Integrated Circuits, Zhejiang University, Hangzhou 310027, China.
  12. Bin Yu: College of Integrated Circuits, Zhejiang University, Hangzhou 310027, China. ORCID

Abstract

Emerging neuromorphic hardware promises energy-efficient computing by colocating multiple essential functions at the individual component level. The implementation is challenging due to mismatch between the characteristics of multifunctional devices and neural networks. Here, we demonstrate an artificial synapse based on a 2D ��-phase indium selenide that exhibits integrated perception-and-computing-in-memory functions in a single-transistor setup, serving as a basic building block for reservoir computing. Extending to the array architecture enables concurrent image-sensing and memory. Further, we implement multimode deep-reservoir computing with adjustable nonlinear transformation and multisensory fusion using this core device. In the lane-keeping-assistance task for an unmanned vehicle, the system demonstrates ���10 times lower energy consumption and significantly boosted data throughput compared to the state-of-the-art graphics processors. The demonstrated perception-and-computing-in-memory (PCIM) functions at a single-transistor level shows the feasibility of implementing ultrascalable, resource-efficient hardware for brain-inspired computing.

Keywords

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Created with Highcharts 10.0.0computingfunctionsperception-and-computing-in-memoryhardwarelevelartificialsynapse2D��-phaseindiumselenidesingle-transistorreservoirEmergingneuromorphicpromisesenergy-efficientcolocatingmultipleessentialindividualcomponentimplementationchallengingduemismatchcharacteristicsmultifunctionaldevicesneuralnetworksdemonstratebasedexhibitsintegratedsetupservingbasicbuildingblockExtendingarrayarchitectureenablesconcurrentimage-sensingmemoryimplementmultimodedeep-reservoiradjustablenonlineartransformationmultisensoryfusionusingcoredevicelane-keeping-assistancetaskunmannedvehiclesystemdemonstrates���10timeslowerenergyconsumptionsignificantlyboosteddatathroughputcomparedstate-of-the-artgraphicsprocessorsdemonstratedPCIMshowsfeasibilityimplementingultrascalableresource-efficientbrain-inspiredMultimodalFerroelectricTransistorIntegratedPerception-and-Computing-in-MemoryFunctionsReservoirComputingferroelectrics

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